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| MC100EPT25 Differential LVECL/ECL to LVTTL Translator The MC100EPT25 is a Differential LVECL/ECL to LVTTL translator. This device requires +3.3V, -3.3V to -5.2V, and ground. The small outline 8-lead SOIC package and the single gate of the EPT25 make it ideal for applications which require the translation of a clock or data signal. The VBB output allows the EPT25 to also be used in a single-ended input mode. In this mode the VBB output is tied to the D input for a non-inverting buffer or the D input for an inverting buffer. If used, the VBB pin should be bypassed to ground via a 0.01mF capacitator. http://onsemi.com MARKING DIAGRAMS* 8 8 1 SO-8 D SUFFIX CASE 751 1 8 8 1 A L Y W TSSOP-8 DT SUFFIX CASE 948R 1 = Assembly Location = Wafer Lot = Year = Work Week HR25 ALYW HPT25 ALYW * * * * * * * * * * * * * * 1.1ns Typical Propagation Delay 275MHz Fmax (Clock bit stream, not pseudo-random) Differential LVECL/ECL inputs Small Outline SOIC Package 24mA TTL outputs Flow Through Pinouts Internal Input Resistors: Pulldown on D, Pulldown and Pullup on D Q Output will default LOW with inputs open or at GND ESD Protection: >4000V HBM, >200V MM VBB Output New Differential Input Common Mode Range Moisture Sensitivity Level 1, Indefinite Time Out of Drypack. For Additional Information, See Application Note AND8003/D Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34 Transistor Count = 111 devices VEE 1 LVTTL 8 VCC *For additional information, see Application Note AND8002/D PIN DESCRIPTION PIN Q D, D VCC VBB GND VEE FUNCTION LVTTL Output Differential LVECL Input Pair Positive Supply Output Reference Voltage Ground Negative Supply D 2 7 Q D 3 LVECL 6 NC ORDERING INFORMATION Device Package SO-8 SO-8 TSSOP-8 TSSOP-8 Shipping 98 Units / Rail 2500 / Reel 98 Units / Rail 2500 / Reel MC100EPT25D MC100EPT25DR2 MC100EPT25DT VBB 4 5 GND Figure 1. 8-Lead Pinout (Top View) and Logic Diagram MC100EPT25DTR2 (c) Semiconductor Components Industries, LLC, 2000 1 May, 2000 - Rev. 1 Publication Order Number: MC100EPT25/D MC100EPT25 MAXIMUM RATINGS* Symbol VCC VEE VI Iout IBB TA Tstg JA JC Tsol Parameter Power Supply (Referenced to GND, VEE = -3.3V) Power Supply (Referenced to GND, VCC = +3.3V) Input Voltage (VI not more positive than GND) Output Current VBB Sink/Source Current{ Operating Temperature Range Storage Temperature Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Solder Temperature (<2 to 3 Seconds: 245C desired) Still Air 500lfpm Continuous Surge Value 0 to 3.8 -6.0 to 0 0 to 3.8 50 100 0.5 -40 to +85 -65 to +150 190 130 41 to 44 5% 265 Unit VDC VDC VDC mA mA C C C/W C/W C * Maximum Ratings are those values beyond which damage to the device may occur. { Use for inputs of same package only. DC CHARACTERISTICS, ECL/LVECL (VCC = +3.3V; VEE = -5.5V to -3.0V, GND = 0V) -40C Symbol IEE VIH VIL VBB Characteristic Power Supply Current (Note 1.) Input HIGH Voltage Single Ended (Note 4.) Input LOW Voltage Single Ended (Note 4.) Output Voltage Reference Min 8.0 -1165 -1810 -1550 -1450 Typ 16 Max 25 -880 -1625 -1350 0.0 150 D D 0.5 -150 0.5 -150 Min 8.0 -1165 -1810 -1550 -1450 25C Typ 16 Max 25 -880 -1625 -1350 0.0 150 0.5 -150 Min 8.0 -1165 -1810 -1550 -1450 85C Typ 16 Max 25 -880 -1625 -1350 0.0 150 Unit mA mV mV mV V A A VIHCMR Input HIGH Voltage Common Mode Range (Note 3.) IIH IIL Input HIGH Current Input LOW Current VEE+2.0 VEE+2.0 VEE+2.0 NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 1. (VCC = +3.3V, GND = 0V, VEE = -3.3V), all other pins floating. 2. All loading with 500 ohms to GND, CL = 20pF. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. 4. Input and output parameters vary 1:1 with VCC. http://onsemi.com 2 MC100EPT25 TTL OUTPUT DC CHARACTERISTICS (VCC = 3.3V 0.3V; GND = 0V; VEE = -3.3V 0.3V; TA = -40C to 85C) Symbol ICCH ICCL VOH VOL Characteristic Power Supply Current (Outputs set to HIGH) Power Supply Current (Outputs set to LOW) Output HIGH Voltage (IOH = -3.0mA) (Note 5.) Output LOW Voltage (IOL = 24mA) (Note 5.) Min 6.0 7.0 2.2 0.5 Typ 10 12 Max 14 17 Unit mA mA V V IOS Output Short Circuit Current -130 -60 mA NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 5. All loading with 500 ohms to GND, CL = 20pF. AC CHARACTERISTICS (VCC = 3.3V 0.3V; GND = 0V) -40C Symbol fmax tPLH, tPHL tSK+ + tSK- - tSKPP tJITTER VPP Characteristic Maximum Toggle Frequency Propagation Delay to Output Differential Output-to-Output Skew++ Output-to-Output Skew- - Part-to-Part Skew (Note 6.) Cycle-to-Cycle Jitter Input Voltage Swing (Differential) (Note 7.) 100 Min 275 800 1200 60 25 500 TBD 800 1200 100 450 900 1800 Typ Max Min 275 800 1100 60 25 500 TBD 800 600 1100 1200 750 1400 100 450 900 1600 25C Typ Max Min 275 800 1100 60 25 500 TBD 800 600 1100 1200 750 1400 1600 85C Typ Max Unit MHz ns ps ps mV ps tr Output Rise/Fall Times Q, Q 450 600 750 tf 900 1160 1400 (0.8V - 2.0V) 6. Skews are measured between outputs under identical conditions. 7. 200mV input guarantees full logic swing at the output. http://onsemi.com 3 MC100EPT25 PACKAGE DIMENSIONS SO-8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-06 ISSUE T A 8 D 5 C E 1 4 H 0.25 M B M h B C e A SEATING PLANE X 45 _ NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ q L 0.10 A1 B 0.25 M CB S A S q http://onsemi.com 4 MC100EPT25 PACKAGE DIMENSIONS TSSOP-8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R-02 ISSUE A 8x K REF 0.10 (0.004) M 0.15 (0.006) T U S 2X TU S V S L/2 8 5 L 1 PIN 1 IDENT 4 B -U- 0.25 (0.010) M 0.15 (0.006) T U S A -V- F DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ C 0.10 (0.004) -T- SEATING PLANE D -W- G DETAIL E DIM A B C D F G K L M http://onsemi.com 5 MC100EPT25 Notes http://onsemi.com 6 MC100EPT25 Notes http://onsemi.com 7 MC100EPT25 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. 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